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? semiconductor components industries, llc, 2012 august, 2012 ? rev. 1 1 publication order number: ncp6332/d NCP6332B, ncp6332c 3mhz, 1.2a synchronous buck converter high efficiency, low ripple, adjustable output voltage the NCP6332B/c, a family of synchronous buck converters, which is optimized to supply different sub systems of portable applications powered by one cell li ? ion or three cell alkaline/nicd/nimh batteries. the devices are able to deliver up to 1.2 a on an external adjustable voltage. operation with 3 mhz switching frequency allows employing small size inductor and capacitors. input supply voltage feedforward control is employed to deal with wide input voltage range. synchronous rectification and automatic pwm/pfm power save mode offer improved system ef ficiency. the NCP6332B/c is in a space saving, low profile 2.0 x 2.0 x 0.75 mm wdfn ? 8 package. features ? 2.3 v to 5.5 v input voltage range ? external adjustable voltage ? up to 1.2 a output current ? 3 mhz switching frequency ? synchronous rectification ? automatic power save (NCP6332B) or external mode selection (ncp6332c) ? enable input ? power good output option (NCP6332B) ? soft start ? over current protection ? active discharge when disabled ? thermal shutdown protection ? wdfn ? 8, 2 x 2 mm, 0.5 mm pitch package ? maximum 0.8mm height for super thin applications ? this is a pb ? free device typical applications ? cellular phones, smart phones, and pdas ? portable media players ? digital still cameras ? wireless and dsl modems ? usb powered devices ? point of load ? game and entertainment system wdfn8 case 511be marking diagram http://onsemi.com 1 ax = specific device code m = date code = pb ? free package ax m 1 (*note: microdot may be in either location) pinout 2 4 fb sw 3 agnd 7 5en avin 6 mode/pg 9 1 pgnd 8 pvin (top view) see detailed ordering, marking and shipping information in the package dimensions section on page 2 of this data sheet. ordering information www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCP6332B, ncp6332c http://onsemi.com 2 1uh vo = 0.6v to vin cout 10uf pgnd fb pvin en sw agnd avin pg cin 10uf rpg 1m vin = 2.3v to 5.5v power good enable r1 r2 cfb NCP6332B 1uh vo = 0.6v to vin cout 10uf pgnd fb pvin en sw agnd avin mode cin 10uf vin = 2.3v to 5.5v mode enable r1 r2 cfb ncp6332c (a) power good output option (NCP6332B) (b) external mode selection (ncp6332c) figure 1. typical application circuits pin description pin name type description 1 pgnd power ground power ground for power, analog blocks. must be connected to the system ground. 2 sw power output switch power pin connects power transistors to one end of the inductor. 3 agnd analog ground analog ground analog and digital blocks. must be connected to the system ground. 4 fb analog input feedback voltage from the buck converter output. this is the input to the error amplifier. this pin is connected to the resistor divider network between the output and agnd. 5 en digital input enable of the ic. high level at this pin enables the device. low level at this pin disables the device. 6 pg/mode digital output pg pin is for NCP6332B with power good option. it is open drain output. low level at this pin indicates the device is not in power good, while high impedance at this pin indicates the device is in power good. mode pin is for ncp6332c with mode external selection option. high level at this pin forces the device to operate in forced pwm mode. low level at this pin enables the device to operate in automatic pfm/pwm mode for power saving function. 7 avin analog input analog supply. this pin is the analog and the digital supply of the device. an optional 1 f or lar- ger ceramic capacitor bypasses this input to the ground. this capacitor should be placed as close as possible to this input. 8 pvin power input power supply input. this pin is the power supply of the device. a 10 f or larger ceramic capacit- or must bypass this input to the ground. this capacitor should be placed as close a possible to this input. 9 pad exposed pad exposed pad. must be soldered to system ground to achieve power dissipation performances. this pin is internally unconnected ordering information device marking package shipping ? NCP6332Bmtaatbg af wdfn8 (pb ? free) 3000 / tape & reel ncp6332cmtaatbg ae wdfn8 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCP6332B, ncp6332c http://onsemi.com 3 pwm / pfm control reference voltage l cout 1uh 10uf logic control & current limit & thermal shutdown cin 10uf rpg 1m uvlo vin vo power good enable pvin 8 sw 2 pgnd 1 en 5 mode/pg 6 fb 4 avin 7 agnd 3 r1 r2 cfb mode pg error amp figure 2. functional block diagram maximum ratings rating symbol value unit min max input supply voltage to gnd v pvin , v avin ? 0.3 7.0 v switch node to gnd v sw ? 0.3 7.0 v en, pg/mode to gnd v en , v pg ? 0.3 7.0 v fb to gnd v fb ? 0.3 2.5 v human body model (hbm) esd rating are (note 1) esd hbm 2000 v machine model (mm) esd rating (note 1) esd mm 200 v latchup current (note 2) i lu ? 100 100 ma operating junction temperature range (note 3) t j ? 40 125 c operating ambient temperature range t a ? 40 85 c storage temperature range t stg ? 55 150 c thermal resistance junction ? to ? top case (note 4) r jc 12 c/w thermal resistance junction ? to ? board (note 4) r jb 30 c/w thermal resistance junction ? to ? ambient (note 4) r ja 62 c/w power dissipation (note 5) p d 1.6 w moisture sensitivity level (note 6) msl 1 ? stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this device series contains esd protection and passes the following tests: human body model (hbm) 2.0 kv per jedec standard: jesd22 ? a114. machine model (mm) 200 v per jedec standard: jesd22 ? a115. 2. latchup current per jedec standard: jesd78 class ii. 3. the thermal shutdown set to 150 c (typical) avoids potential irreversible damage on the device due to power dissipation. 4. the thermal resistance values are dependent of the pcb heat dissipation. board used to drive these data was an 80 x 50 mm ncp 6332evb board. it is a multilayer board with 1 once internal power and ground planes and 2 ? once copper traces on top and bottom of the board. if the copper trances of top and bottom are 1 once too, r jc = 11 c/w, r jb = 30 c/w, and r ja = 72 c/w. 5. the maximum power dissipation (pd) is dependent on input voltage, maximum output current and external components selected. 6. moisture sensitivity level (msl): 1 per ipc/jedec standard: j ? std ? 020a. www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCP6332B, ncp6332c http://onsemi.com 4 electrical characteristics (v in = 3.6 v, v out = 1.8 v, l = 1 h, c = 10 f, typical values are referenced to t j = 25 c, min and max values are referenced to t j up to 125 c, unless other noted.) symbol characteristics test conditions min typ max unit supply voltage v in input voltage v in range (note 10) 2.3 ? 5.5 v supply current i q v in quiescent supply current en high, no load, no switching, pfm mode en high, no load, forced pwm mode ? ? 30 5 ? ? a ma i sd v in shutdown current en low ? ? 1 a output voltage v out output voltage range (note 7) 0.6 ? v in v v fb fb voltage pwm mode 594 600 606 mv fb voltage in load regulation v in = 3.6 v, i out from 200 ma to i outmax , pwm mode (note 7) ? ? 0.5 ? %/a fb voltage in line regulation i out = 200 ma, v in from max (v nom + 0.5 v, 2.3 v) to 5.5 v, pwm mode (note 7) ? 0 ? %/v d max maximum duty cycle (note 7) ? 100 ? % output current i outmax output current capability (note 7) 1.2 ? ? a i lim output peak current limit 1.5 1.9 2.2 a voltage monitor v inuv ? v in uvlo falling threshold ? ? 2.3 v v inhys v in uvlo hysteresis 60 ? 2 0 0 mv v pgl power good low threshold v out falls down to cross the threshold (percentage of fb voltage) (note 8) 87 90 92 % v pghys power good hysteresis v out rises up to cross the threshold (percentage of power good low threshold (v pgl ) voltage) (note 8) 0 3 5 % td pgh1 power good high delay in start up from en rising edge to pg going high. (note 8) ? 1.15 ? ms td pgl1 power good low delay in shut down from en falling edge to pg going low. (notes 7 and 8) ? 8 ? s td pgh power good high delay in regula- tion from v fb going higher than 95% nominal level to pg going high. not for the first time in start up. (notes 7 and 8) ? 5 ? s td pgl power good low delay in regulation from v fb going lower than 90% nominal level to pg going low. (notes 7 and 8) ? 8 ? s vpg_l power good pin low voltage voltage at pg pin with 5 ma sink current (note 8) ? ? 0.3 v pg_lk power good pin leakage current 3.6 v at pg pin when power good valid (note 8) ? ? 100 na integrated mosfets r on_h high ? side mosfet on resistance v in = 3.6 v (note 9) v in = 5 v (note 9) ? 140 130 200 ? m r on_l low ? side mosfet on resistance v in = 3.6 v (note 9) v in = 5 v (note 9) ? 110 100 140 ? m 7. guaranteed by design, not tested in production. 8. power good function is for NCP6332B devices only. 9. maximum value applies for t j = 85 c. 10. operation above 5.5 v input voltage for extended periods may affect device reliability. www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCP6332B, ncp6332c http://onsemi.com 5 electrical characteristics (v in = 3.6 v, v out = 1.8 v, l = 1 h, c = 10 f, typical values are referenced to t j = 25 c, min and max values are referenced to t j up to 125 c, unless other noted.) symbol unit max typ min test conditions characteristics switching frequency f sw normal operation frequency 2.7 3.0 3.3 mhz soft start t ss soft ? start time time from en to 90% of output voltage target ? 0.4 1 ms control logic v en_h en input high voltage 1.1 ? ? v v en_l en input low voltage ? ? 0.4 v v en_hys en input hysteresis ? 270 ? mv i en_bias en input bias current 0.1 1 a v mode_h mode input high voltage (note 11) 1.1 ? ? v v mode_l mode input low voltage (note 11) ? ? 0.4 v v mode_hys mode input hysteresis (note 11) ? 270 ? mv i mode_bias mode input bias current (note 11) 0.1 1 a output active discharge r_dis internal output discharge resistance from sw to pgnd 75 500 700 thermal shutdown t sd thermal shutdown threshold ? 150 ? c t sd_hys thermal shutdown hysteresis ? 25 ? c 11. mode function is for ncp6332c devices only. www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCP6332B, ncp6332c http://onsemi.com 6 typical operating characterestics 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 2.5 3 3.5 4 4.5 5 5.5 v in , input voltage (v) figure 3. standby current vs. input voltage (en = low, t a = 25 c) i sd , v in shutdown current ( a) figure 4. standby current vs. temperature (en = low, v in = 3.6 v) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 ? 50 ? 25 0 25 50 75 100 125 150 t a , ambient temperature ( c) 0 10 20 30 40 50 60 2.5 3 3.5 4 4.5 5 5.5 v in , input voltage (v) i q , v in quiescent current ( a) figure 5. quiescent current vs. input voltage (en = high, open loop, v out = 1.8 v, t a = 25 c) 0 10 20 30 40 50 60 ? 50 ? 25 0 25 50 75 100 125 150 i sd , v in shutdown current ( a) i q , v in quiescent current ( a) t a , ambient temperature ( c) 50 55 60 65 70 75 80 85 90 95 100 1 10 100 1000 10000 figure 6. quiescent current vs. temperature (en = high, open loop, v out = 1.8 v, v in = 3.6 v) i out , output current (ma) efficiency (%) v in = 2.7 v v in = 5.5 v v in = 3.6 v figure 7. efficiency vs. output current and input voltage (v out = 1.05 v, t a = 25 c) 50 55 60 65 70 75 80 85 90 95 100 1 10 100 1000 10000 efficiency (%) i out , output current (ma) v in = 2.7 v v in = 5.5 v v in = 3.6 v figure 8. efficiency vs. output current and input voltage (v out = 1.8 v, t a = 25 c) www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCP6332B, ncp6332c http://onsemi.com 7 typical operating characterestics figure 9. efficiency vs. output current and input voltage (v out = 3.3 v, t a = 25 c) figure 10. efficiency vs. output current and input voltage (v out = 4 v , t a = 25 c) figure 11. load regulation vs. output current and input voltage (v out = 1.8 v, t a = 25 c) figure 12. load regulation vs. output current and temperature (v in = 3.6 v, v out = 1.8 v). figure 13. output ripple voltage in pwm mode (v in = 3.6 v, v out = 1.8 v, i out = 1 a, l=1 h, c out = 10 f) figure 14. output ripple voltage in pfm mode (v in = 3.6 v, v out = 1.8 v, i out = 10 ma, l=1 h, c out = 10 f) 50 55 60 65 70 75 80 85 90 95 100 1 10 100 1000 10000 i out , output current (ma) efficiency (%) v in = 3.6 v v in = 5.5 v 50 55 60 65 70 75 80 85 90 95 100 1 10 100 1000 10000 v in = 4.5 v v in = 5.5 v i out , output current (ma) efficiency (%) i out , output current (ma) v out , output voltage (v) v in = 5.5 v v in = 3.6 v i out , output current (ma) v out , output voltage (v) t a = 25 c t a = 85 c t a = ? 40 c v in = 2.7 v vout 4 mv sw time: 500 ns / div vout 25 mv sw 10 mv / div 5 mv / div 2 v / div time: 5 s / div 2 v / div 1.77 1.78 1.79 1.8 1.81 1.82 1.83 0 200 400 600 800 1000 1200 1.77 1.78 1.79 1.8 1.81 1.82 1.83 0 200 400 600 800 1000 1200 www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCP6332B, ncp6332c http://onsemi.com 8 typical operating characterestics figure 15. load transient response (v in = 3.6 v, v out = 1.8 v, i out = 200 ma to 1200 ma, l = 1 h, c out = 10 f) figure 16. power up sequence and inrush current in input (v in = 3.6 v, v out = 1.8 v, i out = 0 a, l = 1 h, c out = 10 f) figure 17. power up sequence and power good (v in = 3.6 v, v out = 1.8 v, i out = 0 a, l = 1 h, c out = 10 f) figure 18. power down sequence and active output discharge (v in = 3.6 v, v out = 1.8 v, i out = 0 a, l = 1 h, c out = 10 f) en 5 v/ div sw 5 v / div vout 1.0 v / div iin 100 ma / div 70 ma time: 100 s / div vout 1.0 v / div en 5 v/ div sw 2 v / div time: 1 ms / div pg 5 v / div vout 1.0 v / div en 5 v/ div sw 2 v / div time: 200 s / div pg 5 v / div 64 mv 60 mv 200 ma 1200 ma vout 100 mv / div iout 1 a / div sw 5 v / div time 20 ms / div www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCP6332B, ncp6332c http://onsemi.com 9 detailed description general the NCP6332B/c, a family of voltage ? mode synchronous buck converters, which is optimized to supply different sub ? systems of portable applications powered by one cell li ? ion or three cell alkaline/nicd/nimh batteries. the devices are able to deliver up to 1.2 a on an external adjustable voltage. operation with 3 mhz switching frequency allows employing small size inductor and capacitors. input supply voltage feedforward control is employed to deal with wide input voltage range. synchronous rectification and automatic pwm/pfm power save mode offer improved system efficiency. operation mode selection (ncp6332c) for ncp6332c with an external mode selection option, high level (above 1.1 v) at mode pin forces the device to operate in forced pwm mode. low level (below 0.4 v) at this pin enables the device to operate in automatic pfm/pwm mode for power saving function. pwm mode operation in medium and heavy load range, the inductor current is continuous and the device operates in pwm mode with fixed switching frequency, which has a typical value of 3 mhz. in this mode, the output voltage is regulated by on ? time pulse width modulation of an internal p ? mosfet. an internal n ? mosfet operates as synchronous rectifier and its turn ? on signal is complimentary to that of the p ? mosfet. pfm mode operation in light load range, the inductor current becomes discontinuous and the device automatically operates in pfm mode with an adaptive fixed on time and variable switching frequency. in this mode, the output voltage is regulated by pulse frequency modulation of the internal p ? mosfet, and the switching frequency is almost proportional to the loading current. the internal n ? mosfet operates as synchronous rectifier after each on pulse of the p ? mosfet with a very small negative current limit. when the load increases and the inductor current becomes continuous, the controller automatically turns back to the fixed ? frequency pwm mode operation. undervoltage lockout the input voltage vin must reach or exceed 2.4 v (typical) before the NCP6332B/c enables the converter output to begin the start up sequence. the uvlo threshold hysteresis is typically 100 mv. enable the NCP6332B/c has an enable logic input pin en. a high level (above 1.1 v) on this pin enables the device to active mode. a low level (below 0.4 v) on this pin disables the device and makes the device in shutdown mode. there is an internal filter with 5 s time constant. the en pin is pulled down by an internal 10 na sink current source. in most of applications, the en signal can be programmed independently to vin power sequence. en pg vout 95% 90% 1.1v 0.4v 300us 1.15ms 8us 5us 8us active discharge 8us 100us figure 19. power good and active discharge timing diagram power good output (NCP6332B) for NCP6332B with a power good output, the device monitors the output voltage and provides a power good output signal at the pg pin. this pin is an open ? drain output pin. to indicate the output of the converter is established, a power good signal is available. the power good signal is low when en is high but the output voltage has not been established. once the output voltage of the converter drops out below 90% of its regulation during operation, the power good signal is pulled low and indicates a power failure. a 5% www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCP6332B, ncp6332c http://onsemi.com 10 hysteresis is required on power good comparator before signal going high again. soft ? start a soft start limits inrush current when the converter is enabled. after a minimum 300 s delay time following the enable signal, the output voltage starts to ramp up in 100 s (for external adjustable voltage devices) or with a typical 10 v/ms slew rate (for fixed voltage devices). active output discharge an output discharge operation is active in when en is low. a discharge resistor (500 typical) is enabled in this condition to discharge the output capacitor through sw pin. cycle ? by ? cycle current limitation the NCP6332B/c protects the device from over current with a fixed ? value cycle ? by ? cycle current limitation. the typical peak current limit ilmt is 1.6 a. if inductor current exceeds the current limit threshold, the p ? mosfet will be turned off cycle ? by ? cycle. the maximum output current can be calculated by i max i lmt v out v in v out 2 v in f sw l (eq. 1) where vin is input supply voltage, vout is output voltage, l is inductance of the filter inductor, and f sw is 3 mhz normal switching frequency. thermal shutdown the NCP6332B/c has a thermal shutdown protection to protect the device from overheating when the die temperature exceeds 150 c. after the thermal protection is triggered, the fault state can be ended by re ? applying vin and/or en when the temperature drops down below 125 c. www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCP6332B, ncp6332c http://onsemi.com 11 application information output filter design considerations the output filter introduces a double pole in the system at a frequency of f lc 1 2 l c (eq. 2) the internal compensation network design of the NCP6332B/c is optimized for the typical output filter comprised of a 1.0 h inductor and a 10 f ceramic output capacitor, which has a double pole frequency at about 50 khz. other possible output filter combinations may have a double pole around 50 khz to have optimum operation with the typical feedback network. normal selection range of the inductor is from 0.47 h to 4.7 h, and normal selection range of the output capacitor is from 4.7 f to 47 f. inductor selection the inductance of the inductor is determined by given peak ? to ? peak ripple current il_pp of approximately 20% to 50% of the maximum output current iout_max for a trade ? off between transient response and output ripple. the inductance corresponding to the given current ripple is l v in v out v out v in f sw i l_pp (eq. 3) the selected inductor must have high enough saturation current rating to be higher than the maximum peak current that is i l_max i out_max i l_pp 2 (eq. 4) the inductor also needs to have high enough current rating based on temperature rise concern. low dcr is good for efficiency improvement and temperature rise reduction. table 1 shows some recommended inductors for high power applications and table 2 shows some recommended inductors for low power applications. table 1. list of recommended inductors for high power applications manufacturer part number case size (mm) l ( h) rated current (ma) (inductance drop) structure murata lqh44pn2r2mp0 4.0 x 4.0 x 1.8 2.2 2500 ( ? 30%) wire wound murata lqh44pn1r0np0 4.0 x 4.0 x 1.8 1.0 2950 ( ? 30%) wire wound murata lqh32pnr47nnp0 3.0 x 2.5 x 1.7 0.47 3400 ( ? 30%) wire wound table 2. list of recommended inductors for low power applications manufacturer part number case size (mm) l ( h) rated current (ma) (inductance drop) structure murata lqh44pn2r2mj0 4.0 x 4.0 x 1.1 2.2 1320 ( ? 30%) wire wound murata lqh44pn1r0nj0 4.0 x 4.0 x 1.1 1.0 2000 ( ? 30%) wire wound tdk vls201612et ? 2r2 2.0 x 1.6 x 1.2 2.2 1150 ( ? 30%) wire wound tdk vls201612et ? 1r0 2.0 x 1.6 x 1.2 1.0 1650 ( ? 30%) wire wound output capacitor selection the output capacitor selection is determined by output voltage ripple and load transient response requirement. for a given peak ? to ? peak ripple current il_pp in the inductor of the output filter, the output voltage ripple across the output capacitor is the sum of three ripple components as below. v out_pp v out_pp(c) v out_pp(esr) v out_pp(esl) (eq. 5) where vout_pp(c) is a ripple component by an equivalent total capacitance of the output capacitors, vout_pp(esr) is a ripple component by an equivalent esr of the output capacitors, and vout_pp(esl) is a ripple component by an equivalent esl of the output capacitors. in pwm operation mode, the three ripple components can be obtained by v out_pp(c) i l_pp 8 c f sw (eq. 6) v out_pp(esr) i l_pp esr (eq. 7) v out_pp(esl) esl esl l v in (eq. 8) and the peak ? to ? peak ripple current is i l_pp v in v out v out v in f sw l (eq. 9) www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCP6332B, ncp6332c http://onsemi.com 12 in applications with all ceramic output capacitors, the main ripple component of the output ripple is vout_pp(c). so that the minimum output capacitance can be calculated regarding to a given output ripple requirement vout_pp in pwm operation mode. c min i l_pp 8 v out_pp f sw (eq. 10) input capacitor selection one of the input capacitor selection guides is the input voltage ripple requirement. to minimize the input voltage ripple and get better decoupling in the input power supply rail, ceramic capacitor is recommended due to low esr and esl. the minimum input capacitance regarding to the input ripple voltage vin_pp is c in_min i out_max d d 2 v in_pp f sw (eq. 11) where d v out v in (eq. 12) in addition, the input capacitor needs to be able to absorb the input current, which has a rms value of i in_rms i out_max d d 2 (eq. 13) the input capacitor also needs to be sufficient to protect the device from over voltage spike, and normally at least a 4.7 f capacitor is required. the input capacitor should be located as close as possible to the ic on pcb. table 3. list of recommended input capacitors and output capacitors manufacturer part number case size height max (mm) c ( f) rated voltage (v) structure murata grm21br60j226me39, x5r 0805 1.4 22 6.3 mlcc tdk c2012x5r0j226m, x5r 0805 1.25 22 6.3 mlcc murata grm21br61a106ke19, x5r 0805 1.35 10 10 mlcc tdk c2012x5r1a106m, x5r 0805 1.25 10 10 mlcc murata grm188r60j106me47, x5r 0603 0.9 10 6.3 mlcc tdk c1608x5r0j106m, x5r 0603 0.8 10 6.3 mlcc murata grm188r60j475ke19, x5r 0603 0.87 4.7 6.3 mlcc design of feedback network for NCP6332B/c devices with an external adjustable output voltage, the output voltage is programmed by an external resistor divider connected from v out to fb and then to agnd, as shown in the typical application schematic figure 1(a). the programmed output voltage is v out v fb 1 r 1 r 2 (eq. 14) where v fb is equal to the internal reference voltage 0.6 v, r1 is the resistance from v out to fb, which has a normal value range from 50 k to 1 m and a typical value of 220 k for applications with the typical output filter. r2 is the resistance from fb to agnd, which is used to program the output voltage according to equation (14) once the value of r1 has been selected. a capacitor cfb needs to be employed between the v out and fb in order to provide feedforward function to achieve optimum transient response. normal value range of cfb is from 0 to 100 pf, and a typical value is 15 pf for applications with the typical output filter and r1 = 220 k . table 4 provides reference values of r1 and cfb in case of different output filter combinations. the final design may need to be fine tuned regarding to application specifications. table 4. reference values of feedback networks (r1 and cfb) for output filter combinations (l and c) r1 (k ) l ( h) cfb (pf) 0.47 0.68 1 2.2 3.3 4.7 c ( f) 4.7 220 220 220 220 330 330 3 5 8 15 15 22 10 220 220 220 220 330 330 8 10 15 27 27 39 22 220 220 220 220 330 330 15 22 27 39 47 56 47 220 220 220 220 330 330 33 39 47 68 68 82 www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCP6332B, ncp6332c http://onsemi.com 13 layout considerations electrical layout considerations good electrical layout is a key to make sure proper operation, high efficiency, and noise reduction. electrical layout guidelines are: ? use wide and short traces for power paths (such as pvin, vout, sw, and pgnd) to reduce parasitic inductance and high ? frequency loop area. it is also good for efficiency improvement. ? the device should be well decoupled by input capacitor and input loop area should be as small as possible to reduce parasitic inductance, input voltage spike, and noise emission. ? sw node should be a large copper pour, but compact because it is also a noise source. ? it would be good to have separated ground planes for pgnd and agnd and connect the two planes at one point. directly connect agnd pin to the exposed pad and then connect to agnd ground plane through vias. try best to avoid overlap of input ground loop and output ground loop to prevent noise impact on output regulation. ? arrange a ?quiet? path for output voltage sense and feedback network, and make it surrounded by a ground plane. thermal layout considerations good thermal layout helps high power dissipation from a small package with reduced temperature rise. thermal layout guidelines are: ? the exposed pad must be well soldered on the board. ? a four or more layers pcb board with solid ground planes is preferred for better heat dissipation. ? more free vias are welcome to be around ic and/or underneath the exposed pad to connect the inner ground layers to reduce thermal impedance. ? use large area copper especially in top layer to help thermal conduction and radiation. ? do not put the inductor to be too close to the ic, thus the heat sources are distributed. a vin gnd vout gnd cin cin ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? ??? www.datasheet.net/ datasheet pdf - http://www..co.kr/
NCP6332B, ncp6332c http://onsemi.com 14 package dimensions wdfn8 2x2, 0.5p case 511be issue a notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. ??? ??? ??? a d e b c 0.10 pin one 2x reference 2x top view side view bottom view l d2 e2 c c 0.10 c 0.10 c 0.08 a1 seating plane 8x note 3 b 8x 0.10 c 0.05 c a b b dim min max millimeters a 0.70 0.80 a1 0.00 0.05 b 0.20 0.30 d 2.00 bsc d2 1.50 1.70 e 2.00 bsc e2 0.80 1.00 e 0.50 bsc l 0.20 0.40 1 4 8 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 pitch 1.00 2.30 1 dimensions: millimeters 0.50 8x note 4 0.30 8x detail a a3 0.20 ref a3 a detail b l1 detail a l alternate constructions ?? ?? ?? ??? 0.15 outline package e recommended k 0.25 ref 5 1.70 k on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncp6332/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative www.datasheet.net/ datasheet pdf - http://www..co.kr/

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